The paper “Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics, by Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich, published by IEEE in 2006, available from http://hal-lirmm.ccsd.cnrs.fr/docs/00/09/36/90/PDF/DTIS06-53.pdf” describes a scan test system. Scan architectures are expensive in power consumption. In the paper, the issues of excessive peak power consumption during scan testing are discussed. Taking care of high current levels during the test cycle (i.e. between launch and capture) is highly relevant to avoid noise phenomena such as IR-drop or ground bounce.
While many techniques have evolved to address power minimization during the functional mode of operation, it is required to manage power during test mode. Circuit activity is substantially higher during test than during functional mode, and the resulting excessive power consumption can cause structural damage or severe decrease in reliability of the circuit under test. In the context of scan testing, the problem of excessive power during test is much more severe as the application of each test pattern requires a large number of shift operations that contributes to unnecessarily increasing the switching activity. Power consumption must be analyzed from two different perspectives. Average power consumption is, as the name implies, the average power utilized over a long period of operation or a large number of clock cycles. Instantaneous power is the amount of power required during a small instant of time such as the portion of a clock cycle immediately following the system clock rising or falling edge. The peak power is the maximum value of the instantaneous power. Average power consumption during scan testing can be controlled by reducing the scan clock frequency a well known solution used in industry. In contrast, peak power consumption during scan testing is independent of the clock frequency and hence is much more difficult to control.
Scan patterns in some designs may consume much more peak power over the normal mode and may result in failures during manufacturing test. Combined with high speed, excessive peak power during test also causes high rates of current (di/dt) in the power and ground rails and hence leads to excessive power and ground noise (VDD or Ground bounce). This may erroneously change the logic state of some circuit nodes or flip-flops and cause some good dies to fail the test, thus leading to unnecessary loss of yield. Similarly, IR-drop and crosstalk effects are phenomena that may show up an error in test mode but not in functional mode. With high peak current demands during test, the voltages at some gates in the circuit are reduced. This causes these gates to exhibit higher delays, possibly leading to test fails and yield loss.
The problem of excessive peak power during scan testing can be divided in two sub-problems: excessive peak power during load/unload cycles and excessive peak power during the test cycle, denoted as TC and defined as the clock cycle between launch and capture. Several techniques have been proposed for reducing test power dissipation during load/unload cycles. Most of them are initially targeted for reducing average power but they usually can reduce peak power as well. Some low power scan architectures reduce the clock rate on the scan cells during shift operations thus reducing the power consumption without increasing the test time. Other solutions consist in assigning don't care bits of the deterministic test cubes used during test in such a way that it can reduce the peak power.
Compared to load/unload cycles, peak power reduction during TC is a less researched area. In the above paper a proposal is based on power-aware assignment of don't care bits in deterministic test patterns. The proposal addresses the power consumption during shift by controlling the pattern's logic states.
However, in the above system, a problem of the scan test patterns is that, during the shift mode (in the load/unload cycles), the excessive power consumption limits the maximum scan clock.